And man, this "bug" is so exotic I have to explain it (warning: your head may explode):
This is a summary of events related to clocks and LCD that happen from reset:
- The SPL initializes the PLL and all system clocks.
- The system loader initializes the LCD and shows the Dingoo Digital splash screen.
- Either the system loader or the ccpmp.bin program that it loads initialize again the system clocks.
This is what happens in the original firmware:
- The SPL code initializes system clocks: PLL 336MHz, PLL output 336/2=168MHz.
- The system loader initializes the LCD clock generator. It programs the divider to obtain 16.8MHz. It accounts for the "divide by two" configuration and thus the required divider for the LCD is 10 (168MHz / 10 = 16.8MHz).
- The system loader (or ccpmp.bin) initializes again the system clocks. As the configuration of the system clocks is the same set in step (1), nothing changes, in particular the LCD clock.
- The dual boot SPL initializes system clocks: PLL 336MHz, PLL output 336MHz (not divided by two !!!).
- The system loader initializes the LCD clock generator. It programs the divider to obtain 16.8MHz. As the PLL output is not divided by two, the required divider for the LCD is 21 (336MHz / 21 = 16MHz, which is the best possible approximation to 16.8MHz).
- The system loader (or ccpmp.bin) initializes again the system clocks, but now, something changes: the PLL output is programmed to be divided by two. As the LCD clock divider remains unchanged, the net result is that the LCD clock is divided by two, resulting in 8MHz.
IMPORTANT: something similar was happening with the USB clock. That might explain the effect of plugging the USB cable that some users notices, though I can't think of what is actually happening. Also, I can't explain why some users hardly notice the slowdown while others say it's unbearable.
Not sure if this was the only thing that needed to be fixed. I'm still investigating in the GPIO differences I noticed.
I have already fixed it and plan to repackage it all again and make another release. However, there's an interesting dilemma here: some users are extremely happy because the reduced LCD pixel clock seems to fix tearing in some games/emulators. I all for fixing it because:
- I don't have time to play. I'm too busy coding :-)
- The whole idea is to leave the original firmware unchanged.
- It is not ok for some users. We need something that works for everybody.
/* Timing setting */
pclk = 16800000; /* Pixclk */
pll_div = (REG_CPM_CPCCR & CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */
pll_div = pll_div ? 1 : 2 ;
val = (__cpm_get_pllout() / pll_div) / pclk;
if (val > 0x1ff)
val = 0x1ff;
REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* Update divide */